Substrate for mounting a semiconductor

ABSTRACT

A substrate ( 1 ) is formed from a non-electrically conducting material and is for mounting a semiconductor chip ( 10 ). The substrate has a semiconductor chip mounting portion ( 6 ). A number of first electrically conducting contact portions ( 5 ) are formed on the surface of the material and associated with the mounting portion ( 6 ). A second electrically conducting contact portion ( 3 ) is formed on the surface of the material, and the second electrically conducting contact portion ( 3 ) is adapted to be coupled to testing equipment. A number of electrically conducting paths ( 4 ) are formed on the surface of the material. The conducting paths ( 4 ) electrically connect the second electrically conducting contact portion ( 3 ) to a minority of the first electrically conducting contact portions ( 5 ).

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to International Application No.PCT/SG01/00046 filed Mar. 30, 2001 entitled “A SUBSTRATE FOR MOUNTING ASEMICONDUCTOR CHIP.”

BACKGROUND Technical Field

This invention relates to a substrate, and especially a non-conductivesubstrate, for mounting a semiconductor chip.

The advantage of using an electrically non-conducting substrate formounting semiconductor chips (or dies) is that it is possible to formthe electrically conducting contacts (or bondfingers), to which theinput/output pads of the die are connected, in any position on thesurface of the substrate and the contacts are insulated from each otherby virtue of the non-conductive nature of the substrate. This contrastswith a conventional metal lead frame, in which the electrical contactneeds to be electrically isolated by removing material from the leadframe so as to form an air gap which electrically insulates adjacentcontacts.

Each input/output pad (or bond pad) of the die is electrically connectedto a corresponding bondfinger by a metal wire that is bonded using awire bonding machine, between each of the bond pad and the bondfinger.With a non-conductive substrate, the testing of the bonds is usuallyperformed by means of an electrically conducting contact surface usuallylocated on an edge of the substrate. This contact surface corresponds tothe mold gate in a subsequent molding operation, and so is sometimesreferred to as the mold gate. The mold gate is clamped in the wirebonder and forms an electrical connection with the wire bonder to permitthe bonds to be tested during the wire bonding operation.

The mold gate is connected to each of the bondfingers by electricallyconducting paths (or traces) formed on the surface of the substrate. Asthere can be in excess of a hundred separate bondfingers for onesemiconductor chip, this requires a corresponding number of traces toconnect all the bondfingers to the mold gate.

One of the problems with this arrangement is that where the chip is awireless communication chip such as a radio frequency (RF) chip, thesetraces can act as antennae that may adversely affect the operation ofthe RF chip. Therefore, for a RF chip design, it is preferable not tohave traces extending from the bondfingers to the mold gate. However,this results in the problem that it is not possible to test the wirebonds during the wire bond operation.

SUMMARY

In accordance with the present invention, a substrate comprising anon-electrically conducting material for mounting a semiconductor chipcomprises a semiconductor chip mounting portion, a number of firstelectrically conducting contact portions formed on the surface of thematerial and associated with the mounting portion, a second electricallyconducting contact portion formed on the surface of the material, thesecond electrically conducting contact portion being adapted to becoupled to wire bonding apparatus, and a number of electricallyconducting paths formed on the surface of the material to electricallyconnect the second electrically conducting contact portion to a minorityof the first electrically conducting contact portions.

An advantage of the invention is that by forming an electricallyconducting path between the second contact portion and a minority of thefirst contact portions, it is possible to test the bonds on the contactpad on the die and the first electrically conducting contact surfaces,as in most the chip designs, each bond pad on the chip is electricallycoupled to the other pads, for example via transistor, while reducingthe antennae effect of the paths on a wireless communication packageddevice.

Typically, less than 10% of the first contact portions are connected tothe second contact portion.

Preferably, a maximum of ten of the first contact portions are connectedto the second contact portion, more preferably a maximum of five firstcontact portions are connected to the second contact portions, and mostpreferably there is only one electrically conducting path, the oneelectrically conducting path electrically connecting only one firstcontact portion to the second contact portion.

Typically, the substrate is for mounting a wireless communication chip,such as a RF chip.

Typically, the substrate may comprise a number of mounting portions,each mounting portion having a number of first contact portionsassociated therewith.

BRIEF DESCRIPTION OF THE DRAWINGS

An example of a substrate for mounting a semiconductor chip inaccordance with the invention will now be described with reference tothe accompanying drawings, in which:

FIG. 1 is a plan view of a substrate showing a matrix arrangement ofmounting areas for a semiconductor chip;

FIG. 2 is a detailed plan view of one of the semiconductor chip mountingareas; and

FIG. 3 is a schematic cross-sectional view showing wire bond testingduring the wire bond operation for a semiconductor chip mounted on oneof the mounting areas.

DETAILED DESCRIPTION

FIG. 1 shows a substrate 1 having a matrix array of mounting areas (orzones) 2. The substrate 1 is formed from an electrically insulating corematerial, which is typically a glass fibre and epoxy resin mixture.Common core materials are for example, BT or FR-4. Each of the zones 2is adapted to have a semiconductor chip (or die) mounted thereon andincludes a number of metal alloy pads (or bondfingers) 5 which areconnected to input/output pads 11 of a semiconductor chip 10 mounted onthe mounting zone 2 via electrically conducting wires (see FIG. 3). Thearrangement of the bondfingers 5 in a zone 2 is shown in more detail inFIG. 2.

An electrically conducting contact portion (or mold gate) 3 is formed onan edge of the substrate 1. An electrically conducting trace 4electrically connects the contact portion 3 to one bondfinger 5 a ineach of the mounting zones 2. The bondfinger 5 a is also connected tothe central metal traces which form a die attach area 6. The bondfinger5 a is the first bondfinger in the wire bonding process to be bonded toa bond pad 11 on a semiconductor chip 10 mounted in the mounting zone 2.

In use, the chip 10 is mounted on a die attach area 6 of the mountingzone 2 using a die attach material 12. The substrate 1 is then mountedin a wire bonder (not shown) and the contact portion 3 clamped in thewire bonder to form an electrical connection with the wire bonder.Firstly, the wire bonder bonds an end of a wire 13 to a first bond pad11 a on the chip 10 using the capillary 15. The capillary is then movedto the first bondfinger 5 a and also bonds the wire 13 to the firstbondfinger 5 a. The wire bonder then clamps the wire 13 in a wire clamp16 and lifts the capillary 15 away from the bondfinger 5 a. If the wire13 has been properly bonded to the bondfinger 5 a, the wire 13 willbreak as the capillary is lifted leaving a wire bond 14 a extendingbetween the first bond pad 11 a and the first bondfinger 5 a.

The capillary 15 of the wire bonder then moves to a second bond pad 11 band bonds the free end of the wire 13 to the second bond pad 11 b on thechip 10. After the bond is made and the capillary is lifted way from thebond pad 11 b, the wire bonder injects a current into the wire 13. Ifthe bond to the bond pad 11 b is good, current will flow through thewire 13 into the bond pad 11 b. As each of the bond pads 11 areelectrically coupled to each other within the chip, typically via atransistor arrangement, the current will flow to the first bond pad 11a, through the first bond wire 14 a, the first bondfinger 5 a, the trace4 to the contact portion 3 where the current is detected by the wirebonder which is electrically coupled to the contact portion 3. Hence,the wire bonder can detect whether the bond made on the second bond pad11 b is good. It should be noted that the electrical coupling of thebond pads 11 within the chip 10 is a common feature of most chip designsand is conventional.

After the bond to the second bond pad 11 b has been tested, the wirebonder moves the capillary 15 to the second bondfinger 5 a and bonds thewire 13 to the second bondfinger 5 b. The wire bonder then clamps thewire 13 using the wire clamp 16 and lifts the wire clamp 16 and thecapillary 15 away from the second bondfinger 5 b. If the bond to thesecond bondfinger 5 b is good, lifting the capillary 15 and wire clamp16 away from the second bond finger 5 b causes the wire 13 to break.Hence, if the wire bonder then injects a current into the wire 13, nocurrent will be detected at the contact portion 3. However, if the bondto the second bondfinger 5 b is not good and the wire does not break butthe bond lifts off the bondfinger 5 b when the wire clamp 16 andcapillary 15 are lifted, a current injected into the wire 13 will bedetected at the contact portion 3.

The same process is then repeated on each of the other wire bonds madeon the other bond pads 11 and bondfingers 5 until all the necessaryconnections has been made between the bond pads 11 on the chip 10 andthe bondfingers on the substrate 1.

Therefore, the invention has the advantage of enabling conventional wirebond testing to be performed on a semiconductor chip mounted on asubstrate, without requiring an electrically conducting path (or trace)to extend from each bond finger to the contact portion 3, as only onetrace is required to connect one bondfinger for each chip molded onsubstrate 1. This has the advantage that the performance of a wirelesscommunication chip, such as a RF chip, is not likely to be adverselyaffected, as a single trace will in most cases have a negligible affecton the performance or operation of the chip.

1. A substrate comprising a non-electrically conducting material formounting a semiconductor chip, the substrate comprising a semiconductorchip mounting portion, a number of first electrically conducting contactportions formed on the surface of the material and associated with themounting portion and adapted to be wire bonded to contacts of thesemiconductor chip, a second electrically conducting contact portionformed on the surface of the material, the second electricallyconducting contact portion being adapted to be coupled to testingequipment, and a number of electrically conducting paths formed on thesurface of the material, the conducting paths electrically connectingthe second electrically conducting contact portion to a minority of thefirst electrically conducting contact portions, the substrate includingfirst electrically conducting contact portions which are not connectedby a conducting path to an electrically conducting contact portionadapted to be coupled to testing equipment during a wire bondingoperation performed on that first electrically conducting contactportion.
 2. A substrate according to claim 1, wherein less than 10% ofthe first contact portions are connected to the second contact portion.3. A substrate according to claim 1, wherein a maximum of ten of thefirst contact portions are connected to the second contact portion.
 4. Asubstrate according to claim 3, wherein a maximum of five first contactportions are connected to the second contact portions.
 5. A substrateaccording to claim 4, wherein there is only one electrically conductingpath, the one electrically conducting path electrically connecting onlyone first contact portion to the second contact portion.
 6. A substrateaccording to claim 1, wherein one of the first contact portionsconnected to the second contact portion is coupled to a ground contacton the substrate.
 7. A substrate according to claim 6, wherein theground contact is on the mounting portion.
 8. A substrate according toclaim 1, wherein the substrate is for mounting a wireless communicationchip.
 9. A substrate according to claim 1, wherein the substratecomprises a number of mounting portions, each mounting portion having anumber of first contact portions associated therewith.
 10. A method ofelectrically connecting an integrated circuit to a substrate comprisinga non-electrically conducting material for mounting a semiconductorchip, the substrate comprising a semiconductor chip mounting portion, anumber of first electrically conducting contact portions formed on thesurface of the material and associated with the mounting portion, asecond electrically conducting contact portion formed on the surface ofthe material, the second electrically conducting contact portion beingadapted to be coupled to testing equipment, and a number of electricallyconducting paths formed on the surface of the material, the conductingpaths electrically connecting the second electrically conducting contactportion to a minority of the first electrically conducting contactportions, the method comprising: coupling the second electricallyconducting contact portion to said testing equipment; mounting asemiconductor chip on the substrate; performing a wire bonding operationon one of the first contact portions to which the second electricallyconductive contact portion is connected by the conducting paths, whilemonitoring the current on the second electrically conductive contactportion; and performing a wire bonding operation on one of the firstcontact portions to which the second electrically conductive contactportion is not connected by the conducting paths, while monitoring thecurrent on the second electrically conductive contact portion.
 11. Amethod according to claim 10, wherein less than 10% of the first contactportions are connected to the second contact portion.
 12. A methodaccording to claim 10, wherein a maximum often of the first contactportions are connected to the second contact portion.
 13. A methodaccording to claim 12, wherein a maximum of five first contact portionsare connected to the second contact portions.
 14. A method according toclaim 13, wherein there is only one electrically conducting path, theone electrically conducting path electrically connecting only one firstcontact portion to the second contact portion.
 15. A method according toclaim 10, wherein one of the first contact portions connected to thesecond contact portion is coupled to a ground contact on the substrate.16. A method according to claim 15, wherein the ground contact is on themounting portion.
 17. A method according to claim 10, wherein a wirelesscommunication chip is subsequently mounted on the substrate.
 18. Amethod according to claim 10, wherein the substrate comprises a numberof mounting portions, each mounting portion having a number of firstcontact portions associated therewith.